dec: 25 hex: 19 bin: 11001
The Buffer Cell, is an array logic gate. Array gates have gate logic as well as 1 or more pass-through wires. They are also slightly taller than normal gates.
|Circuit Plate +
Wired Plate +
Platformed Plate +
The Buffer Cell has a total of 4 inputs and outputs. All IOs in this gate act as wires. The wire connecting the front and back is the bottom wire and the left and right wire is the top wire.
The Buffer cell acts much like 2 separate wires in a single block. This gate can allow one 'wire' to transverse between the front and back, and the other between left and right without crossing the signals. If the bottom wire is powered, a signal is conducted upwards to the top wire. When the bottom one is unpowered, the top returns to its natural state. Unlike traditional gates, there is no delay when passing a signal between inputs; it functions identically to wires.
|v4.0.0||Added the Buffer Cell.|
Issues pertaining to "Buffer Cell" are maintained on the ProjectRed Github page. Report issues there.